1. Field of the Invention
This invention relates to an integrated circuit (IC) device and fabrication thereof, and more particularly relates to a memory device and a method for fabricating the same.
2. Description of Related Art
A memory is a semiconductor device for storing information or data. As the computer microprocessors become more and more powerful, programs and operations executed by the software are increased correspondingly. Consequentially, the demand for high storage capacity memories is getting more.
Among various types of memory products, a non-volatile memory allows multi-time data programming, reading and erasing operations, and the data stored therein can be retained even after the power to the memory is terminated. With these advantages, the non-volatile memory has become one of the most widely adopted memories for personal computers and electronic equipment.
Electrically programmable and erasable non-volatile memory technologies based on charge storage structures and known as Electrically Erasable Programmable Read-Only Memory (EEPROM) and flash memory are used in various modern applications. A flash memory is designed with an array of memory cells that can be independently programmed and read. Traditional flash memory cells store charges in a floating gate, but another type of flash memory uses a charge-trapping structure, such as a layer of non-conductive SiN material, instead of a floating gate including a conductive material. When a charge-trapping cell is programmed, charges are trapped and do not move through the non-conductive layer. The charges are retained by the charge trapping layer until the cell is erased, retaining the data state without continuously applied electrical power. Charge-trapping cells can be operated as two-sided cells. That is, because the charges do not move through the non-conductive charge trapping layer, the charges can be localized on different charge-trapping sites. On the other words, in the flash memory devices with the use of the charge-trapping structure, more than one bit of information is stored in each memory cell.
A single memory cell can be programmed to store two physically separated bits in the trapping structure, in the form of a concentration of charges near the source and another concentration of charges near the drain. Programming of the memory cell can be performed by Channel Hot Electron (CHE) injection, which generates hot electrons in the channel region. Some of the hot electrons gain enough energy to be trapped in the charge-trapping structure. By interchanging the biases applied to the source and drain terminals, charges are trapped either in a portion of the charge-trapping structure near the source region, near the drain region, or both.
Usually, one of four distinct combinations of bits 00, 01, 10 and 11 can be stored in a memory cell having a charge-trapping structure, wherein each combination has a corresponding threshold voltage (Vt). In a read operation, the current flowing through the memory cell varies depending upon the Vt of the cell. Typically, such current has one of four different values each corresponding to a different Vt. Accordingly, by sensing such current, the particular bit combination stored in the cell is determined.
The total available charge range or Vt range may be referred to as the memory operation window. In other words, the memory operation window is defined by the difference between the program level and the erase level. A large memory operation window is desired as good level separation between states is needed for cell operation. The performance of two-bit memory cells, however, is often degraded by the so-called “second bit effect” in which localized charges in the charge-trapping structure interact with each other. For example, during a reverse read operation, a read bias is applied to the drain terminal and the charge stored near the source region (i.e., a “first bit”) is sensed, then the bit near the drain region (i.e., the “second bit”), however, creates a potential barrier for reading the first bit near the source region. This barrier may be overcome by applying a bias with a suitable magnitude, using the drain-induced barrier lowering (DIBL) effect to suppress the effect of the second bit near the drain region and allow the sensing of the storage status of the first bit. However, when the second bit near the drain region is programmed to a high Vt state and the first bit near the source region is at un-programmed state, the second bit raises this barrier substantially. Thus, as the Vt associated with the second bit increases, the read bias for the first bit becomes insufficient to overcome the potential barrier created thereby, and the Vt associated with the first bit is raised as a result of the higher Vt of the second bit reducing the memory operation window. The second bit effect decreases the memory operation window for 2-bit/cell operation, so there is a need for methods and devices capable of suppressing the second bit effect in memory devices.